The Gap Between Hardware and Software

Interesting read over at EE Times Asia, titled “IC industry addresses multicore, programming software gap“.

An excerpt:

“The semiconductor industry is starting to address what’s being called a software gap between a rising tide of multicore processors and a lack of parallel programming tools and techniques to make use of them.

The gap came into stark focus in the embedded world at the Multicore Expo, where chipmakers Freescale Semiconductor, Intel Corp., MIPS and a handful of silicon startups sketched out directions for their multicore products. Others warned that the industry has its work cut out for it delivering the software that will harness the next-generation chips.”

“There is a major gap between the hardware and the software,” said Eric Heikkila, director of embedded hardware research at Venture Development Corp. (VDC).

About 55 % of embedded system developers surveyed by VDC said they are using or will use multicore processors in the next 12 months. That fact is fueling the company’s projections that the market for embedded multicore processors will grow from about $372 million in 2007 to $2.47 billion in 2011.

In the PC market, the figures are even more dramatic. About 40 % of all processors Intel shipped in 2007 used multiple cores, but that will rise to 95 % in 2011, said Doug Davis, general manager of Intel’s embedded group.

But on the software side, vendors reported that only about 6 % of their tools were ready for parallel chips in 2007, a figure that will only rise to 40 % in 2011, VDC said. As much as 85 % of all embedded programming is now done in C or C++, languages that are “difficult to optimize for multicore,” said Heikkila.

Standardization

The Multicore Association announced at the Multicore Expo it has completed work on an applications programming interface for communications between cores, and is now working to define a standard for embedded virtualization.

“The ultimate goal of every computer scientist is to create a new language, but my personal view is we should not do it this time around,” said Wen-mei Hwu, a veteran researcher in parallel programming and professor of engineering at the University of Illinois at Urbana-Champaign, referring to a flowering of languages developed for big parallel computers two decades ago, many of which never gained traction. I believe there will be new language constructs in C/C++ to support some of the new frameworks people will develop, but even these constructs, if we are not careful, will not be widely adopted,” Hwu said. “Ultimately, I think we will make a small amount of extensions to C, but I think it’s too early.”

On-chip fabric

For their part, Freescale and Intel sketched out design trends they see on the horizon for their multicore chips.

“Freescale is now sampling the first dual-core versions of its PowerQuicc processors, aimed at telecom OEMs. The chips are part of a family that will eventually scale to 32-core devices”, said Dan Cronin, VP of R&D for Freescale’s networking division.

The processors will use a new on-chip interconnect fabric. They will also embed in hardware a hypervisor, a kind of low-level scheduling unit, co-developed with IBM according to specs set in the Power.org group. “Freescale will release an open source reference design for companies that want to build virtualization software that taps into the hypervisor”, Cronin said.

[Source: VMBlog]